Arbiter circuit and method of carrying out arbitration

ABSTRACT

A method of carrying out arbitration in a packet exchanger including an input buffer temporarily storing a packet having arrived at an input port, and a packet switch which switches a packet between a specific input port and a specific output port, includes the steps of (a) concurrently carrying out a first plurality of sequences in each of the sequences basic processes for at least one of the input buffer and the output port are carried out in a predetermined order, and (b) making an allowance in each of the sequences for packets to be output through output ports at different times from one another.

BACKGROUND OF THE INVENTION

[0001] 1. FIELD OF THE INVENTION

[0002] The invention relates to an arbiter circuit used in a packetexchanger, and more particularly to an arbiter circuit used in a packetexchanger which switches a packet between a specific input port and aspecific output port by virtue of packet communication technique such asasynchronous transfer mode (ATM). The invention relates further to amethod of carrying out arbitration in such a packet exchanger.

[0003] 2. DESCRIPTION OF THE RELATED ART

[0004]FIG. 1 is a block diagram of a conventional packet exchanger.

[0005] The illustrated packet exchanger is comprised of input ports500-1 to 500-n, output ports 501-1 to 501-n, a packet switch 5 whichswitches a packet between the input ports 500-1 to 500-n and the outputports 501-1 to 501-n, input buffers 7-1 to 7-n temporarily accumulatingpackets having arrived at the input ports 500-1 to 500-n, an arbitercircuit 6, and input highways 502-1 to 502-n connecting the inputbuffers 7-1 to 7-n to the packet switch 5.

[0006] As illustrated in FIG. 2, the packet switch 5 is designed to turnon or off intersections 50 at each of which transmission lines extendingin a grid intersect with each other.

[0007] The packet switch 5 illustrated in FIG. 2 is accompanied with aproblem that when a plurality of the input ports concurrently transmitpackets to a specific output port, packets would make collision with oneanother, resulting in destruction of data carried by the packets.Accordingly, it is necessary in the packet switch 5 to allow only oneinput port to transmit a packet to a specific output port at certaintiming.

[0008] As illustrated in FIG. 1, each of the input buffers 7-1 to 7-n isdesigned to include an input device 72, an output device 73, and logicalqueues 71-1 to 71-n in association with the output ports 501-1 to 501-n.The input device 72 accumulates packets having arrived at the inputports 500-1 to 500-n, in a trail in one of the logical queues 71-1 to71-n in dependence on destination of the queue. The output device 73takes a packet out of a head of the one of the logical queues 71-1 to71-n, and transmits the packet to the packet switch 5.

[0009] The input buffers 7-1 to 7-n transmit output request signals600-1 to 600-n to the arbiter circuit 6, respectively. The outputrequest signals 600-1 to 600-n indicate of which output port among theoutput ports 501-1 to 501-n a packet accumulated in the input buffers7-1 to 7-n is directed.

[0010] The arbiter circuit 6 decides input and output ports betweenwhich a packet is to be switched in the packet switch 5 such that thepacket does not make collision with other packets. After making such adecision, the arbiter circuit 6 transmits output allowance signals 601-1to 601-n indicative of the decision, to the input buffers 7-1 to 7-n.

[0011] Arbitration algorithm for deciding input and output ports betweenwhich a packet is to be switched is suggested, for instance, in“Analysis to scheduling algorithm in input buffer type ATM switch”,Electronic Information Communication Society, B-6-20, 1998 (hereinafter,called “article 1”) or “Analysis to High Capacity Packet Switch”,Electronic Information Communication Society, SSE98-160 (hereinafter,called “article 2”).

[0012] In accordance with the algorithm suggested in the article 1,output ports to which a cell accumulated in an input buffer is directedare searched, and one of output ports not yet occupied by any inputbuffers is selected. Such an output port is selected generally inaccordance with the round-robin selection process.

[0013] The above-mentioned selection step is carried out for all ofinput buffers. That is, a basic process in which an output port to whicha packet is transmitted from a certain input buffer is selected amongoutput ports not yet occupied by any input buffers is carried out toinput buffers in a predetermined order. In general, such a basic processis carried out starting from a smaller identification number of inputbuffers.

[0014] Hereinafter, the above-mentioned step is called input sequentialarbitration, and a series of steps for carrying out the above-mentionedbasic processes in a predetermined number is called an input sequence.

[0015]FIG. 3 is a flow-chart showing steps of carrying out the inputsequence in the input sequential arbitration. Hereinbelow is explainedthe input sequence in the input sequential arbitration, with referenceto FIG. 3.

[0016] First, an order in input buffers is determined in step S41.

[0017] Then, all output ports are caused vacant in step S42.

[0018] Then, a variable K is substituted by 0 in step S43.

[0019] Then, an output port to which a K-th input buffer transmits apacket is selected among vacant output ports in step S44.

[0020] Thereafter, 1 is added to the variable K in step S45.

[0021] Then, the variable K is judged whether greater than (N-1) in stepS46. If the variable K is not greater than (N-1) (NO in step S46), thesteps S44 to S46 are repeated. If the variable K is greater than (N-1)(YES in step S46), the input sequence is finished.

[0022] In accordance with the algorithm suggested in the article 2,input buffers accumulating a cell which is to be transmitted to anoutput port are searched, and one of input buffers not yet receiving anallowance to transmit a packet to any one of output ports is selected.Such an input buffer is selected generally in accordance with theround-robin selection process.

[0023] The above-mentioned selection step is carried out for all ofoutput ports. That is, a basic process in which an input buffer to beallowed to transmit a packet to a certain output port is selected amonginput buffers not having an allowance to transmit a packet is carriedout to output buffers in a predetermined order. In general, such a basicprocess is carried out starting from a smaller identification number ofoutput buffers.

[0024] Hereinafter, the above-mentioned step is called output sequentialarbitration, and a series of steps for carrying out the above-mentionedbasic processes in a predetermined number is called an output sequence.

[0025]FIG. 4 is a flow-chart showing steps of carrying out the outputsequence in the output sequential arbitration. Hereinbelow is explainedthe output sequence in the output sequential arbitration, with referenceto FIG. 4.

[0026] First, an order in output ports is determined in step S51.

[0027] Then, all input buffers are caused vacant in step S52.

[0028] Then, a variable K is substituted by 0 in step S53.

[0029] Then, an input buffer to be allowed to transmit a packet to aK-th output port is selected among vacant input buffers in step S54.

[0030] Thereafter, 1 is added to the variable K in step S55.

[0031] Then, the variable K is judged whether greater than (N-1) in stepS56. If the variable K is not greater than (N-1) (NO in step S56), thesteps S54 to S56 are repeated. If the variable K is greater than (N-1)(YES in step S56), the output sequence is finished.

[0032]FIG. 5 is a timing chart showing a timing at which the input andoutput sequences are carried out in the input and output sequentialarbitration.

[0033] In the conventional arbitration, after an input or outputsequence has been started, an allowance for transmitting a packet at acertain time is made. After an input or output sequence has beenfinished, a next input or output sequence is made start. In order totransmit a packet at a maximum rate corresponding to a line rate, eachof the input or output sequences is required to be completed within aunit period of time defined as a period of time necessary fortransmitting a packet from an input buffer or a period of time necessaryfor a packet to pass through a line.

[0034] As mentioned earlier, the conventional packet exchanger wasrequired to complete the input or output sequence in a unit period oftime. In each of the input and output sequences, the basic process forindividual input buffer or output port is carried out for all inputbuffers and output ports. Hence, the number of the basic processes to becarried out in each of the sequences is increased as the number of portsin the packet exchanger increases.

[0035] However, since a unit period of time remains unchanged whenpackets have the same size and a line rate remains unchanged, a time forcarrying out the individual basic process has to be decreased down to1/X, if the number of ports in the packet exchanger is multiplied by Xwherein X is an integer equal to or greater than 2.

[0036] Accordingly, if the packet exchanger is designed to have anincreased capacity, the arbiter circuit carrying out the arbitration hasto be designed to have a process capacity thereof multiplied by X inrate, resulting in a significant increase in fabrication cost.

[0037] In addition, even if a plurality of classes classified by itspriority, there the conventional packet exchanger does not have analgorithm for efficiently accumulating the classes.

[0038] Japanese Unexamined Patent Publication No. 7-297831 has suggestedan input buffer type ATM switch circuit including a plurality of inputbuffers at an input of an ATM switch. In the suggested input buffer typeATM switch circuit, cells are grouped into a plurality of levels independence on delay of the cells. Each of the cells stores therein aperiod of time for which the cell can be stored in the input buffer foreach identifiers of the cell.

[0039] The suggested circuit is comprised of a plurality of cell queuesassociated with each of the delay levels, a cell counter counting thenumber of cells accumulated in the input buffer, first means forgenerating arbitration data weighed in accordance with the delay levelsof the cells, the period of time transmitted from the cell queue, andthe number of the cells accumulated in the input buffer, and secondmeans for, if a cell is requested to be directed to the same output portfrom the input buffers, allowing a cell to be transmitted to the outputport from an input buffer which is most heavily weighed in thearbitration data generated by the first means.

[0040] Japanese Unexamined Patent Publication No. 10-32585 has suggestedan ATM switch controller arranged between an input buffer and an outputbuffer, including a first circuit which monitors how degree the outputbuffer is used and transmits a signal indicative of a degree at whichthe output buffer is used, and a second circuit which arbitrates anoutput cell supplied to the ATM switch from the input buffer, inaccordance with the signal.

[0041] Japanese Patent No. 2894442 (Japanese Unexamined PatentPublication No. 11-68779) has suggested a short cell switch having avariable length, which can process a low-rate voice signal in a shortperiod of time. The short cell switch is comprised of predominantly of ahardware.

[0042] Japanese Unexamined Patent Publication No. 9-321768 has suggestedan ATM exchange including an input buffer temporarily accumulating anATM cell input through a certain input line, a cross-bar type switchexchanging an ATM cell output from the input buffer, and an arbitercircuit providing conditions for turning on or off the cross-bar typeswitch, in accordance with priority provided to FIFO in the inputbuffer. The input buffer includes FIFOs in the number equal to thenumber of output lines in each of input lines, a distributordistributing cells to FIFO associated with an output line numberacquired from header data of the ATM cell, and a selector selecting FIFOfrom which a cell is to be read out, in accordance with a signaltransmitted from the arbiter circuit. The arbiter circuit is comprisedof a sub-arbiter circuit determining FIFO having highest priority, basedon priority level information of FIFOs in the input lines, a masterarbiter circuit carrying out arbitration in competition among the inputlines, and an exchange table register in which correspondence betweeninput line numbers and output line numbers is stored.

[0043] However, the above-mentioned problems remain unsolved even in theabove-mentioned Publications.

SUMMARY OF THE INVENTION

[0044] In view of the above-mentioned problems in the conventionalarbiter circuits, it is an object of the present invention to provide amethod of carrying out arbitration and an arbiter circuit both of whichare capable of increasing a capacity of a packet exchanger even if anarbiter circuit includes a processor having a low process capacity, andefficiently accumulating a plurality of classes classified in accordancewith priority.

[0045] In one aspect of the present invention, there is provided amethod of carrying out arbitration in a packet exchanger including aninput buffer temporarily storing a packet having arrived at an inputport, and a packet switch which switches a packet between a specificinput port and a specific output port, the method including the steps of(a) concurrently carrying out a first plurality of sequences in each ofthe sequences basic processes for at least one of the input buffer andthe output port are carried out in a predetermined order, and (b) makingan allowance in each of the sequences for packets to be output throughoutput ports at different times from one another.

[0046] In the method in accordance with the present invention, thesequences in each of which the basic processes are carried out in anorder of the input buffers are concurrently carried out in the inputsequential arbitration. The number of the sequences to be concurrentlycarried out may be equal to the number of ports in the packet exchanger.In each of the sequences concurrently carried out, an allowance for apacket to be output through an output port at a different time fromother packets is made.

[0047] After a first plurality of sequences has been finished, a secondplurality of sequences may be carried out. The basic process to becarried out for each of the input buffers in each of the sequences arecompleted within a unit period of time defined as a period of timenecessary for an input buffer to output a packet therefrom. In each ofthe sequences, the basic processes are carried out for different inputbuffers in the same unit period of time.

[0048] If the number of ports in a packet exchanger is multiplied by Xfor increasing a capacity of the packet exchanger, the number of thebasic processes to be carried out in each of the sequences is multipliedby X, and the number of the sequences to be concurrently carried out isalso multiplied by X. Since allowances for outputting packets atsuccessive times are made in each of the sequences, it would be possibleto output a packet at a maximum rate corresponding to a line rate, evenif each of the sequences is completed in a period of time AX wherein Aindicates a period of time before increasing a capacity of the packetexchanger.

[0049] The method in accordance with the present invention may beapplied to the output sequential arbitration. The sequences in each ofwhich the basic processes are carried out in an order of the outputports are concurrently carried out in the output sequential arbitration.In each of the sequences concurrently carried out, an allowance for apacket to be output through an output port at a different time fromother packets is made. The basic process to be carried out for each ofthe output ports in each of the sequences is completed within the unitperiod of time. In each of the sequences, the basic processes arecarried out for different output ports in the same unit period of time.Thus, the same advantages obtained in the input sequential arbitrationcan be obtained also in the output sequential arbitration.

[0050] Since the basic processes are carried out for different inputbuffers or output ports at the same timing in the sequences concurrentlycarried out, different unit modules are operated at the same timing ineach of the sequences. If a capacity of a packet exchanger is increasedby increasing the number of ports, the number of the sequences to beconcurrently carried out is increased. However, it would not benecessary to increase a capability of each of the unit modules,resulting in that it would be possible to constitute the arbiter circuitincluding unit modules comprised of processors having a low capability.

[0051] It is preferable that each of the basic processes includes thestep of (c) selecting an output port through which a packet is outputfrom an input port, among output ports not yet occupied by any inputbuffers, the step being to be carried out in input sequentialarbitration in which the basic processes are carried out for the inputbuffers in a predetermined order.

[0052] It is preferable that each of the basic processes includes thestep of selecting an input buffer to be allowed to output a packetthrough an output port, among input buffers not yet allowed to do so,the step being to be carried out in output sequential arbitration inwhich the basic processes are carried out for the output ports in apredetermined order.

[0053] It is preferable that the basic process is completed in a unitperiod of time defined as a period of time necessary for the inputbuffers to output a packet, the basic process being carried out for atleast one of the input buffers and the output ports in each of thesequences in the unit period of time.

[0054] The method may further include the step of concurrently carryingout a second plurality of sequences after the first plurality ofsequences have been carried out, in which case, it is preferable thatthe second plurality of sequences is carried out in an order justopposite to an order in which the first plurality of sequences iscarried out.

[0055] This prevents specific input buffers or output ports frompreferentially acquiring an allowance to output a packet, resulting inprevention of significant non-uniformity between the input buffers andthe output ports.

[0056] It is preferable that herein the first plurality of sequencesstarts being carried out at a first time and the second plurality ofsequences starts being carried out at a second time later than the firsttime by a predetermined period of time.

[0057] It is preferable that each of the basic processes includes thesteps of (a) selecting an input buffer to be allowed to output a packethaving a higher priority among packets accumulated in the input buffers,and (b) selecting an input buffer to be allowed to output a packethaving a lower priority among packets accumulated in the input buffers,in which case, the step (a) may be completed in a half of a unit periodof time defined as a period of time necessary for the input buffers tooutput a packet, and the step (b) may be completed in a half of the unitperiod of time.

[0058] This would make it possible to switch packets classified to aplurality of priority classes, in accordance with priority of thepackets.

[0059] For instance, the step (c) includes the steps of (c1) carryingout the basic processes for all of the input buffers with respect to apacket having a higher priority, and (c2) carrying out the basicprocesses for all of the input buffers with respect to a packet having alower priority, in which case, it is preferable that each of the basicprocesses is completed in a half of a unit period of time defined as aperiod of time necessary for the input buffers to output a packet.

[0060] As an alternative, each of the basic processes may be completedin a unit of period of time defined as a period of time necessary forthe input buffers to output a packet, and another sequence starts beingcarried out after the step (c1) have been completed.

[0061] This would make it possible to switch packets classified to aplurality of priority classes, in accordance with priority of thepackets, without necessity of increasing a capacity of the unit modules.

[0062] In another aspect of the present invention, there is provided anarbiter circuit constituting a packet exchanger together with an inputbuffer temporarily storing a packet having arrived at an input port, anda packet switch which switches a packet between a specific input portand a specific output port, the arbiter circuit having functions of (a)concurrently carrying out a first plurality of sequences in each of thesequences basic processes for at least one of the input buffer and theoutput port are carried out in a predetermined order, and (b) making anallowance in each of the sequences for packets to be output throughoutput ports at different times from one another.

[0063] It is preferable that an output port through which a packet isoutput from an input port is selected among output ports not yetoccupied by any input buffers in each of the basic processes which arecarried out for the input buffers in a predetermined order.

[0064] It is preferable that an input buffer to be allowed to output apacket through an output port is selected among input buffers not yetallowed to do so in each of the basic processes which are carried outfor the output ports in a predetermined order.

[0065] It is preferable that the basic process is completed in a unitperiod of time defined as a period of time necessary for the inputbuffers to output a packet, the basic process being carried out for atleast one of the input buffers and he output ports in each of thesequences in the unit period of time.

[0066] The arbiter circuit may further include a function ofconcurrently carrying out a second plurality of sequences after carryingout the first plurality of sequences, in which case, it is preferablethat the arbiter circuit carries out the second plurality of sequencesin an order just opposite to an order in which the arbiter circuitcarries out the first plurality of sequences.

[0067] As an alternative, the arbiter circuit may start carrying out thefirst plurality of sequences at a first time and the second plurality ofsequences at a second time later than the first time by a predeterminedperiod of time.

[0068] It is preferable that the arbiter circuit selects an input bufferto be allowed to output a packet having a higher priority among packetsaccumulated in the input buffers, and then selects an input buffer to beallowed to output a packet having a lower priority among packetsaccumulated in the input buffers, in each of the basic processes, inwhich case, it is preferable that the arbiter circuit selects the inputbuffer in a half of a unit period of time defined as a period of timenecessary for the input buffers to output a packet.

[0069] It is preferable that the arbiter circuit carries out the basicprocesses for all of the input buffers firstly with respect to a packethaving a higher priority, and secondly with respect to a packet having alower priority, in which case, it is preferable that the arbiter circuitcarries out each of the basic processes in a half of a unit period oftime defined as a period of time necessary for the input buffers tooutput a packet.

[0070] It is preferable that the arbiter circuit carries out each of thebasic processes in a unit of period of time defined as a period of timenecessary for the input buffers to output a packet, and starts carryingout another sequence after the basic processes have been completed.

[0071] The arbiter circuit may be designed to include (a) a plurality ofunit modules each associated with at least one of the input buffer andthe output port, each of the unit modules carrying out the basicprocesses, and (b) a signal line connecting the unit modules to oneanother in a ring.

[0072] Each of the unit modules carries out the basic process for theassociated input buffer or output port. After having carried out thebasic process, each of the unit modules transmits data indicative ofoutput ports not yet occupied by the input buffers and data indicativeof the input buffers not yet having an allowance of transmitting apacket, to a next stage unit module through the signal line.

[0073] The arbiter circuit may include (a) a plurality of unit moduleseach associated with at least one of the input buffer and the outputport, each of the unit modules carrying out the basic processes, (b) afirst signal line connecting the unit modules to one another in a ring,a signal being transmitted through the first signal line in a firstdirection, and (c) a second signal line connecting the unit modules toone another in a ring, a signal being transmitted through the secondsignal line in a second direction opposite to the first direction.

[0074] The arbiter circuit may include (a) a plurality of unit moduleseach associated with at least one of the input buffer and the outputport, each of the unit modules carrying out the basic processes, (b) afirst signal line connecting the unit modules to one another in a ring,a signal having a higher priority being transmitted through the firstsignal line, and (c) a second signal line connecting the unit modules toone another in a ring, a signal having a lower priority beingtransmitted through the second signal line.

[0075] It is preferable that the number of the sequences is equal to thenumber of ports in the packet exchanger.

[0076] In still another aspect of the present invention, there isprovided a recording medium readable by a computer, storing a programtherein for causing a computer to carry out the above-mentioned method.

[0077] There is further provided a recording medium readable by acomputer, storing a program therein for causing a computer to act as theabove-mentioned arbiter circuit.

[0078] The advantages obtained by the aforementioned present inventionwill be described hereinbelow.

[0079] In accordance with the present invention, a plurality ofsequences, for instance, equal in number to ports are concurrentlycarried out, and the basic processes are carried out for different inputbuffers or output ports in a unit period of time in each of thesequences. Hence, even if the number of ports in a packet exchanger ismultiplied by X for increasing a capacity of the packet exchanger, andeach of the sequences takes a period of time multiplied by AX to becompleted wherein A indicates a period of time before increasing acapacity of the packet exchanger, by increasing the number of the basicprocesses to be concurrently carried out, it would be possible to outputa packet at a maximum rate corresponding to a line rate, ensuring nonecessity in increasing a rate at which the basic process is to becarried out.

[0080] Regardless of the number of ports in a packet exchanger, thebasic process is completed in the same period of time. In addition, thebasic processes for the same input buffers or output ports are notcarried out at the same time. This ensures no necessity in increasing arate at which the basic process is to be carried out.

[0081] The unit modules associated with the input buffers or outputports may be arranged in a ring through the signal line. Thisarrangement ensures no necessity in increasing a rate at which the unitmodules operate, because the basic processes are completed in the sameperiod of time, even if the number of ports in a packet exchanger isincreased.

[0082] In the method in accordance with the present invention, a secondplurality of sequences may be concurrently carried out, after a firstplurality of sequences have been carried out, in which case, it ispreferable that the second plurality of sequences is carried out in anorder just opposite to an order in which the first plurality ofsequences is carried out.

[0083] This prevents specific input buffers or output ports frompreferentially acquiring an allowance to output a packet, resulting inprevention of significant non-uniformity between the input buffers andthe output ports.

[0084] Since the basic processes are carried out for different inputbuffers or output ports at the same timing in each of the sequencesconcurrently carried out, different unit modules are operated at thesame timing in each of the sequences. Even if a capacity of a packetexchanger is increased by increasing the number of ports, it would notbe necessary to increase a capacity of the unit modules, because thebasic processes are designed to be completed in the same period of time.

[0085] In the output sequential arbitration in accordance with thepresent invention, the arbitration is carried out such that an allowanceto be output through an output port is given to a packet having a higherpriority, in each of the basic processes to be carried out for each ofthe output ports. If such an allowance is not given to a packet having ahigher priority, an allowance to be output through an output port isgiven to a packet having a lower priority.

[0086] This would make it possible to efficiently switch packetsclassified to a plurality of priority classes, in accordance withpriority of the packets.

[0087] In the input sequential arbitration in accordance with thepresent invention, the basic processes are carried out for all of theinput buffers with respect to a packet having a higher priority, andthen, the basic processes are carried out for all of the input bufferswith respect to a packet having a lower priority. Each of the basicprocesses is completed in a half of a unit period of time defined as aperiod of time necessary for the input buffers to output a packet.

[0088] This would make it possible to switch packets classified to aplurality of priority classes, in accordance with priority of thepackets.

[0089] As an alternative, the basic processes are carried out for all ofthe input buffers with respect to a packet having a higher priority, andthen, the basic processes are carried out for all of the input bufferswith respect to a packet having a lower priority, with each of the basicprocesses being completed in the unit of period of time. Anothersequence starts being carried out just when the basic process forpackets having a lower priority has been started.

[0090] This would make it possible to switch packets classified to aplurality of priority classes, in accordance with priority of thepackets, without increasing a capability of the arbiter circuit.

[0091] The above and other objects and advantageous features of thepresent invention will be made apparent from the following descriptionmade with reference to the accompanying drawings, in which likereference characters designate the same or similar parts throughout thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0092]FIG. 1 is a block diagram of a conventional packet exchanger.

[0093]FIG. 2 is a block diagram of a packet switch as a part of thepacket exchanger illustrated in FIG. 1.

[0094]FIG. 3 is a flow-chart showing the steps to be carried out in asequence in the conventional input sequential arbitration.

[0095]FIG. 4 is a flow-chart showing the steps in a sequence to becarried out in the conventional output sequential arbitration.

[0096]FIG. 5 is a timing-chart of a sequence to be carried out in theconventional input or output sequential arbitration.

[0097]FIG. 6 is a timing chart showing a timing at which the inputsequential arbitration is carried out in accordance with the firstembodiment in a packet exchanger.

[0098]FIG. 7 is a flow-chart showing an operation of the inputsequential arbitration carried out in accordance with the firstembodiment.

[0099]FIG. 8 is a timing chart showing a timing at which the inputsequential arbitration is carried out in a packet exchanger having portstwice greater than ports in a packet exchanger in FIG. 6.

[0100]FIG. 9 is a block diagram of an arbiter circuit used in the firstembodiment.

[0101]FIG. 10 is a chart showing an operation of determining an outputport through which a packet is transmitted in the first embodiment.

[0102]FIG. 11 is a block diagram of the arbiter circuit, showing anoperation of determining an output port through which a packet istransmitted in the first embodiment.

[0103]FIG. 12 is a block diagram of the arbiter circuit, showing anoperation of determining an output port through which a packet istransmitted in the first embodiment.

[0104]FIG. 13 is a block diagram of the arbiter circuit, showing anoperation of determining an output port through which a packet istransmitted in the first embodiment.

[0105]FIG. 14 is a block diagram of the arbiter circuit, showing anoperation of determining an output port through which a packet istransmitted in the first embodiment.

[0106]FIG. 15 is a timing chart showing a timing at which the outputsequential arbitration is carried out in the first embodiment.

[0107]FIG. 16 is a flow-chart showing an operation of the outputsequential arbitration in the first embodiment.

[0108]FIG. 17 is a block diagram of an arbiter circuit used in the firstembodiment.

[0109]FIG. 18 is a timing chart showing a timing at which inputsequential arbitration is carried out in accordance with the secondembodiment.

[0110]FIG. 19 is a block diagram of an arbiter circuit used in thesecond embodiment.

[0111]FIG. 20 is a timing chart showing a timing at which inputsequential arbitration is carried out in accordance with the thirdembodiment.

[0112]FIG. 21 is a timing chart showing a timing at which outputsequential arbitration is carried out in accordance with the fourthembodiment.

[0113]FIG. 22 is a timing chart showing a timing at which inputsequential arbitration is carried out in accordance with the fifthembodiment.

[0114]FIG. 23 is a timing chart showing a timing at which outputsequential arbitration is carried out in accordance with the sixthembodiment.

[0115]FIG. 24 is a block diagram of an arbiter circuit used in the sixthembodiment.

[0116]FIG. 25 illustrates examples of recording mediums in which aprogram for carrying out the method in accordance with the presentinvention is to be stored.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0117] Preferred embodiments in accordance with the present inventionwill be explained hereinbelow with reference to drawings.

[0118]FIG. 6 is a timing chart showing a timing at which each ofsequences is carried out in the input sequential arbitration in themethod of carrying out arbitration in a packet exchanger, in accordancewith the first embodiment.

[0119] It is assumed in the first embodiment that a packet exchanger hasfour input and output ports.

[0120] In the first embodiment, four sequences equal in number to theinput and output ports are concurrently carried out. In each of thesequences, an allowance to transmit a packet at different times is made.In the first embodiment, as illustrated in FIG. 6, an allowance totransmit a packet at a time E is made in a first sequence #0, anallowance to transmit a packet at a time F is made in a second sequence#1, an allowance to transmit a packet at a time G is made in a thirdsequence #2, and an allowance to transmit a packet at a time H is madein a fourth sequence #3.

[0121] After the first to fourth sequences #0 to #3 have been completed,next four sequences #4 to #7 concurrently start being carried out. Anallowance to transmit a packet at a time I is made in a fifth sequence#4, an allowance to transmit a packet at a time J is made in a sixthsequence #5, an allowance to transmit a packet at a time K is made in aseventh sequence #6, and an allowance to transmit a packet at a time Lis made in a eighth sequence #7.

[0122] Since allowances to transmit a packet at successive time are madein the first to eighth sequences #0 to #7, even if each of the first toeighth sequences #0 to #7 take a time four times greater than a unitperiod of time for being completed, it would be possible to transmit apacket at a maximum rate corresponding to a line rate.

[0123] In the first sequence #0, the basic process for an input buffer#0 is first carried out, and then, the basic process for an input buffer#1 is carried out. Subsequently, the basic process for an input buffer#2 is first carried out, and then, the basic process for an input buffer#3 is carried out. Since each of the first to fourth sequences #1 to #4may be completed within a period of time equal to a unit period of timemultiplied by 4, each of the basic processes may be completed within aunit period of time.

[0124] Similarly to the first sequence #0, in the second sequence #1,the basic process for an input buffer #1 is first carried out, and then,the basic process for an input buffer #2 is carried out. Subsequently,the basic process for an input buffer #3 is first carried out, and then,the basic process for an input buffer #0 is carried out.

[0125] In the third sequence #2, the basic process for an input buffer#2 is first carried out, and then, the basic process for an input buffer#3 is carried out. Subsequently, the basic process for an input buffer#0 is first carried out, and then, the basic process for an input buffer#1 is carried out.

[0126] In the fourth sequence #3, the basic process for an input buffer#3 is first carried out, and then, the basic process for an input buffer#0 is carried out. Subsequently, the basic process for an input buffer#1 is first carried out, and then, the basic process for an input buffer#2 is carried out.

[0127] As illustrated in FIG. 6, after the first to fourth sequences #0to #3 have been completed, the fifth to eighth sequences #4 to #7 areconcurrently carried out.

[0128] In the fifth sequence #4, the basic process for an input buffer#0 is first carried out, and then, the basic process for an input buffer#1 is carried out. Subsequently, the basic process for an input buffer#2 is first carried out, and then, the basic process for an input buffer#3 is carried out.

[0129] In the sixth sequence #5, the basic process for an input buffer#1 is first carried out, and then, the basic process for an input buffer#2 is carried out. Subsequently, the basic process for an input buffer#3 is first carried out, and then, the basic process for an input buffer#0 is carried out.

[0130] In the seventh sequence #6, the basic process for an input buffer#2 is first carried out, and then, the basic process for an input buffer#3 is carried out. Subsequently, the basic process for an input buffer#0 is first carried out, and then, the basic process for an input buffer#1 is carried out.

[0131] In the eighth sequence #7, the basic process for an input buffer#3 is first carried out, and then, the basic process for an input buffer#0 is carried out. Subsequently, the basic process for an input buffer#1 is first carried out, and then, the basic process for an input buffer#2 is carried out.

[0132] FIG 7 is a flow-chart showing an operation of sequences in theinput sequential arbitration in the first embodiment. In FIG. 7, thesequences are carried out in parallel or independently of each other.

[0133] For instance, when the first sequence #0 starts being carried outin step S1, all output ports are caused vacant in step S2.

[0134] Then, a variable K is substituted by 0 and a variable M issubstituted by 0 both in step S3.

[0135] Then, an output port through which a packet is transmitted froman input buffer #M is selected among vacant output ports in step S4.

[0136] Thereafter, 1 is added to the variable K in step S5. In addition,1 is added to the variable M, and if the variable M is greater than 3(M>3), the variable M is substituted by 0 in step S5.

[0137] Then, the variable K is judged whether greater than 3 (K>3) instep S6. If the variable K is not greater than 3 (NO in step S6), thesteps S4 to S6 are repeated. If the variable K is greater than 3 (YES instep S6), the first sequence #0 is finished in step S7.

[0138] Similarly to the first sequence #0, when the fourth sequence #3starts being carried out in step S11, all output ports are caused vacantin step S12.

[0139] Then, a variable K is substituted by 0 and a variable M issubstituted by 0 both in step S13.

[0140] Then, an output port through which a packet is transmitted froman input buffer #M is selected among vacant output ports in step S14.

[0141] Thereafter, 1 is added to the variable K in step S15. Inaddition, 1 is added to the variable M, and if the variable M is greaterthan 3 (M>3), the variable M is substituted by 0 in step S15.

[0142] Then, the variable K is judged whether greater than 3 (K>3) instep S16. If the variable K is not greater than 3 (NO in step S16), thesteps S4 to S6 are repeated. If the variable K is greater than 3 (YES instep S16), the fourth sequence #3 is finished in step S17.

[0143] Though the second and third sequences #1 and #2 are notillustrated in FIG. 7, they are carried out similarly to the first andfourth sequences #0 and #3.

[0144]FIG. 8 is a timing chart showing a timing at which each of thesequences is carried out in a packet exchanger having ports in a doublednumber for increasing a capacity.

[0145] If a packet exchanger is designed to have ports in a doublednumber for increasing a capacity, the number of the basic processes tobe carried out in each of the first to eighth sequences #0 to #7 wouldbe doubled. However, by doubling the number of the sequences to beconcurrently carried out in accordance with the first embodiment, aperiod of time during which the first to eighth sequences #0 to #7 arecarried out are doubled, resulting in that a period of time necessaryfor carrying out the basic process remains a unit period of time. Thus,if a packet exchanger is designed to have ports in a doubled number forincreasing a capacity, it would be possible to switch a packet at amaximum rate corresponding to a line rate.

[0146] In each of the first to eighth sequences #0 to #7, the basicprocesses are carried out in an order defined by the number of the inputbuffers. However, an input buffer for which the basic process is firstcarried out in one of the first to eighth sequences #0 to #7 isdifferent from an input buffer for which the basic process is firstcarried out in the rest of the sequences.

[0147] Specifically, in the first sequence #0, the basic processes arecarried out for the input buffer #0, the input buffer #1, the inputbuffer #2, the input buffer #3, the input buffer #4, the input buffer#5, the input buffer #6, and the input buffer #7 in this order.

[0148] In the second sequence #1, the basic processes are carried outfor the input buffer #1, the input buffer #2, the input buffer #3, theinput buffer #4, the input buffer #5, the input buffer #6, the inputbuffer #7, and the input buffer #0 in this order.

[0149] In the third sequence #2, the basic processes are carried out forthe input buffer #2, the input buffer #3, the input buffer #4, the inputbuffer #5, the input buffer #6, the input buffer #7, the input buffer#0, and the input buffer #1 in this order.

[0150] In the fourth sequence #3, the basic processes are carried outfor the input buffer #3, the input buffer #4, the input buffer #5, theinput buffer #6, the input buffer #7, the input buffer #0, the inputbuffer #1, and the input buffer #2 in this order.

[0151] In the fifth sequence #4, the basic processes are carried out forthe input buffer #4, the input buffer #5, the input buffer #6, the inputbuffer #7, the input buffer #0, the input buffer #1, the input buffer#2, and the input buffer #3 in this order.

[0152] In the sixth sequence #5, the basic processes are carried out forthe input buffer #5, the input buffer #6, the input buffer #7, the inputbuffer #0, the input buffer #1, the input buffer #2, the input buffer#3, and the input buffer #4 in this order.

[0153] In the seventh sequence #6, the basic processes are carried outfor the input buffer #6, the input buffer #7, the input buffer #0, theinput buffer #1, the input buffer #2, the input buffer #3, the inputbuffer #4, and the input buffer #5 in this order.

[0154] In the eighth sequence #7, the basic processes are carried outfor the input buffer #7, the input buffer #0, the input buffer #1, theinput buffer #2, the input buffer #3, the input buffer #4, the inputbuffer #5, and the input buffer #6 in this order.

[0155] By differentiating an order in which the basic processes arecarried out for the input buffers #0 to #7 in the first to eighthsequences #0 to #7, as mentioned above, the basic processes are carriedout for different input buffers at the same period of time in the firstto eighth sequences #0 to #7.

[0156] For instance, at the first period of time A, the basic processesare carried out for the input buffers #0, #1, #2, #3, #4, #5, #6 and #7in the first, second, third, fourth, fifth, sixth, seventh and eighthsequences #0, #1, #2, #3, #4, #5, #6 and #7, respectively.

[0157]FIG. 9 is a block diagram of the arbiter circuit used in the firstembodiment.

[0158] The arbiter circuit 1 is comprised of first to fourth unitmodules 11, 12, 13 and 14 each associated with each of the first tofourth input buffers, and a signal line 100 connecting the first tofourth unit modules 11 to 14 to one another in a ring.

[0159] The arbiter circuit 1 carries out the input sequentialarbitration. The first to fourth unit modules 11 to 14 receive an outputrequest signal from the associated input buffers. The output requestsignal indicates how many cells the associated input buffer accumulatestherein and further indicates which output port the cells are outputtherethrough.

[0160] By inputting a start signal to the first to fourth unit modules11 to 14 associated with the basic process to be first carried out in asequence, the first to fourth unit modules 11 to 14 carry out the basicprocess to thereby determine an output port through which a packet istransmitted from the associated input buffers.

[0161] For instance, on receipt of the start signal, the first unitmodule 11 starts carrying out the basic process for the first inputbuffer #0. On receipt of the start signal, the second unit module 12starts carrying out the basic process for the second input buffer #1. Onreceipt of the start signal, the third unit module 13 starts carryingout the basic process for the third input buffer #2. On receipt of thestart signal, the fourth unit module 14 starts carrying out the basicprocess for the fourth input buffer #3.

[0162] After the basic process has been completed in each of the firstto fourth unit modules 11 to 14, each of the first to fourth unitmodules 11 to 14 transmits information relating to vacant output portsexcept an output port which has been selected by each of the first tofourth unit modules 11 to 14 and hence occupied by the input buffers, tothe next stage unit module. Each of the next stage unit modules selectsan output port through which a packet is transmitted from the associatedinput buffer, based on the information transmitted from the previousstage unit modules. A sequence is completed at the time when theinformation relating to the vacant output ports circles all around thefirst to fourth unit modules 11 to 14.

[0163] In accordance with a packet exchanger including the arbitercircuit 1 illustrated in FIG. 9, even if the number of ports isincreased in the packet exchanger for increasing a capacity thereof, thenumber of the unit modules connected in a ring is merely increased, andeach of the unit modules still carries out a single sequence in the sameperiod of time. This ensures that it would not be necessary to increasea processing rate, even if a packet exchanger had an increased capacitydue to an increase of ports in number.

[0164] FIGS. 10 to 14 illustrate an operation for selecting an outputport through which a packet is transmitted. In FIGS. 10 to 14, it isassumed that the first to fourth unit modules 11 to 14 are associatedwith the first to fourth input buffers #0 to #3 (not illustrated).

[0165] In an initial condition, each of the first to fourth unit modules11 to 14 stores the number of cells transmittable from the associatedinput buffers #0 to #3 for each of the output ports through which thecells are to be output.

[0166] For instance, as illustrated in FIG. 11, the first unit module 11associated with the first input buffer #0 recognizes that the inputbuffer #0 stores no cell to be directed to a first output port #0, 3cells to be directed to a second output port #1, 5 cells to be directedto a third output port #2, and 2 cells to be directed to a fourth outputport #3.

[0167] Each of the first to fourth unit modules 11 to 14 receivesinformation about the number of cells stored in the associated inputbuffer, from the associated input buffer together with an output requestsignal.

[0168] With reference to FIG. 10, a time base is divided into aplurality of a unit period of times, each of which is identified withidentifiers A to I.

[0169] In a first period of time A, the first to fourth sequences #0 to#3 concurrently start being carried out. In each of the first to fourthsequences #0 to #3, output ports to which packets are transmitted infifth to eighth unit period of times E, F, G and H are determined.

[0170] In the first sequence #0, the basic processes are carried out forthe first input buffer #0, the second input buffer #1, the third inputbuffer #2, and the fourth input buffer #3 in this order.

[0171] In the second sequence #1, the basic processes are carried outfor the second input buffer #1, the third input buffer #2, the fourthinput buffer #3, and the first input buffer #0 in this order.

[0172] In the third sequence #2, the basic processes are carried out forthe third input buffer #2, the fourth input buffer #3, the first inputbuffer #0, and the second input buffer #1 in this order.

[0173] In the fourth sequence #3, the basic processes are carried outfor the fourth input buffer #3, the first input buffer #0, the secondinput buffer #1, and the third input buffer #2 in this order.

[0174] As illustrated in FIG. 11, a sequence start signal is transmittedto the first unit module 11 in the first sequence #0, a sequence startsignal is transmitted to the second unit module 12 in the secondsequence #1, a sequence start signal is transmitted to the third unitmodule 13 in the third sequence #2, and a sequence start signal istransmitted to the fourth unit module 14 in the fourth sequence #3.

[0175] On receipt of the sequence start signal, each of the first tofourth unit modules #0 to #3 carries out the basic processes in each ofthe sequences #0 to #3. In the embodiment, the first unit module 11carries out the basic process for the first input buffer #0 in thesequence #0. At this stage, any output ports are not occupied by theinput buffers in the sequences #0 to #3.

[0176] In the embodiment, it is assumed that the first module #0 givesan allowance to transmit a packet through an output port #1, to thefirst input buffer #0.

[0177] As illustrated in FIG. 12, the first unit module 11 subtracts 1from the number of cells accumulated in the first input buffer #0 anddirected to the second output port #1. In addition, since the first unitmodule 11 has acquired the second output port #1 for the first inputbuffer #0 in the first sequence #0, the first unit module 11 informs thenext stage unit module, that is, the second unit module 12 through thesignal line 100 that only output ports #0, #2 and #3 are vacant in thefirst sequence #0.

[0178] The same operation as carried out in the first unit module 11 iscarried out in the second to fourth unit modules 12 to 14 in differentsequences.

[0179] For instance, on receipt of the sequence start signal, the secondunit module 12 carries out the basic process for the second input buffer#1 in the sequence #1, the third unit module 13 carries out the basicprocess for the third input buffer #2 in the sequence #2, and the fourthunit module 14 carries out the basic process for the fourth input buffer#3 in the sequence #3. Then, after the basic processes have beencompleted, information relating to vacant output ports in each of thefirst to fourth sequences #0 to #3 is transmitted to the next unitmodule.

[0180] Based on the information relating to vacant output ports,transmitted from the upstream unit module, each of the first to fourthunit modules #0 to #3 carries out the basic processes for the associatedinput buffers.

[0181] For instance, as illustrated in FIG. 13, the first unit module 11carries out the basic process to thereby determine an output portthrough which a packet transmitted from the first input buffer #0 istransmitted, based on information 101 relating to vacant output portsfor the sequence #3, transmitted from the upstream unit module or thefourth unit module 13. The information 101 indicates that the first,second and fourth output ports #0, #1 and #3 are vacant, and the thirdoutput port #2 is occupied by the input buffers.

[0182] In the basic process, the first unit module 11 determines thatthe first input buffer #0 transmits a packet through the fourth outputport #3 in the sequence #3. Each of the first to fourth unit modules #0to #3 may determine that the same input buffer transmits a packetthrough the same output port in each of the sequences concurrentlycarried out, because packets are to be transmitted in different periodof times in each of the sequences.

[0183] What is prohibited is that an allowance to transmit a packetthrough a certain output port in the same sequence is made to aplurality of the input buffers.

[0184] For instance, with reference to FIG. 14, the second unit module12 is not allowed to determine that both the first and second inputbuffers #0 and #1 transmit a packet through the second output port #1 inthe sequence #3, even if the second output port #1 is vacant.

[0185] Repeating the above-mentioned operation, each of the sequences isfinished at the time when the information relating to vacant outputports passes through the first to fourth unit modules 11 to 14.

[0186] For instance, when information relating to vacant output portsfor the sequence #0, transmitted from the first unit module 11, arrivesat the fourth unit module 13, the first sequence #0 is finished.

[0187] Since the first to fourth unit modules 11 to 14 start the basicprocess at the different sequences from one another, the first to fourthunit modules 11 to 14 finish the basic process at the differentsequences from one another. Each of the first to fourth unit modules 11to 14 stores which output port an allowance to transmit a packettherethrough is made for the associated input buffer in each of thesequences #0 to #3 until the sequences #0 to #3 are finished, andtransmits an output allowance signal indicative of an output port towhich the above-mentioned allowance is made, to the input buffers #0 to#3 when the sequences #0 to #3 have been finished.

[0188] The output allowance signal is transmitted further to a packetswitch (not illustrated). In each of the sequences #0 to #3, each of theinput buffers #0 to #3 outputs a cell to the allowed output port at aperiod of time associated with the sequences #0 to #3. The packet switchswitches a packet between the input buffers #0 to #3 and the outputports at a period of time associated with the sequences #0 to #3.

[0189] After the first to fourth sequences #0 to #3 have been finished,the fifth to eighth sequences #4 to #7 are carried out for making anallowance to transmit a packet at each of period of times I, J, K and L.The same operation as mentioned above is repeated.

[0190]FIG. 15 is a timing chart showing a timing at which each ofsequences is carried out in the output sequential arbitration in themethod of carrying out arbitration in a packet exchanger, in accordancewith the first embodiment.

[0191] It is assumed that a packet exchanger has four input and outputports.

[0192] In the first embodiment, four sequences equal in number to theinput and output ports are concurrently carried out. In each of thesequences, an allowance to transmit a packet at different times is made.For instance, an allowance to transmit a packet at a time E is made in afirst sequence #0, an allowance to transmit a packet at a time F is madein a second sequence #1, an allowance to transmit a packet at a time Gis made in a third sequence #2, and an allowance to transmit a packet ata time H is made in a fourth sequence #3.

[0193] After the first to fourth sequences #0 to #3 have been completed,next four sequences #4 to #7 concurrently start being carried out. Anallowance to transmit a packet at a time I is made in a fifth sequence#4, an allowance to transmit a packet at a time J is made in a sixthsequence #5, an allowance to transmit a packet at a time K is made in aseventh sequence #6, and an allowance to transmit a packet at a time Lis made in a eighth sequence #7.

[0194] Since allowances to transmit a packet at successive time are madein the first to eighth sequences #0 to #7, even if each of the first toeighth sequences #0 to #7 take a time four times greater than a unitperiod of time for being completed, it would be possible to transmit apacket at a maximum rate corresponding to a line rate.

[0195] In the first sequence #0, the basic process for an input buffer#0 is first carried out, and then, the basic process for an input buffer#1 is carried out. Subsequently, the basic process for an input buffer#2 is first carried out, and then, the basic process for an input buffer#3 is carried out. Since each of the first to fourth sequences #1 to #4may be completed within a period of time equal to a unit period of timemultiplied by 4, each of the basic processes may be completed within aunit period of time.

[0196] Similarly to the first sequence #0, in the second sequence #1,the basic process for an input buffer #1 is first carried out, and then,the basic process for an input buffer #2 is carried out. Subsequently,the basic process for an input buffer #3 is first carried out, and then,the basic process for an input buffer #0 is carried out.

[0197] In the third sequence #2, the basic process for an input buffer#2 is first carried out, and then, the basic process for an input buffer#3 is carried out. Subsequently, the basic process for an input buffer#0 is first carried out, and then, the basic process for an input buffer#1 is carried out.

[0198] In the fourth sequence #3, the basic process for an input buffer#3 is first carried out, and then, the basic process for an input buffer#0 is carried out. Subsequently, the basic process for an input buffer#1 is first carried out, and then, the basic process for an input buffer#2 is carried out.

[0199] As illustrated in FIG. 6, after the first to fourth sequences #0to #3 have been completed, the fifth to eighth sequences #4 to #7 areconcurrently carried out.

[0200] In the fifth sequence #4, the basic process for an input buffer#0 is first carried out, and then, the basic process for an input buffer#1 is carried out. Subsequently, the basic process for an input buffer#2 is first carried out, and then, the basic process for an input buffer#3 is carried out.

[0201] In the sixth sequence #5, the basic process for an input buffer#1 is first carried out, and then, the basic process for an input buffer#2 is carried out. Subsequently, the basic process for an input buffer#3 is first carried out, and then, the basic process for an input buffer#0 is carried out.

[0202] In the seventh sequence #6, the basic process for an input buffer#2 is first carried out, and then, the basic process for an input buffer#3 is carried out. Subsequently, the basic process for an input buffer#0 is first carried out, and then, the basic process for an input buffer#1 is carried out.

[0203] In the eighth sequence #7, the basic process for an input buffer#3 is first carried out, and then, the basic process for an input buffer#0 is carried out. Subsequently, the basic process for an input buffer#1 is first carried out, and then, the basic process for an input buffer#2 is carried out.

[0204]FIG. 16 is a flow-chart showing an operation of sequences in theoutput sequential arbitration in the first embodiment. In FIG. 7, thesequences are carried out in parallel or independently of each other.

[0205] For instance, when the first sequence #0 starts being carried outin step S21, all input buffers are caused vacant in step S22.

[0206] Then, a variable K is substituted by 0 and a variable M issubstituted by 0 both in step S23.

[0207] Then, an input buffer to which an allowance to transmit a packetto an output port #M is to be made is selected among vacant inputbuffers in step S24.

[0208] Thereafter, 1 is added to the variable K in step S25. Inaddition, 1 is added to the variable M, and if the variable M is greaterthan 3 (M>3), the variable M is substituted by 0 in step S25.

[0209] Then, the variable K is judged whether greater than 3 (K>3) instep S26. If the variable K is not greater than 3 (NO in step S26), thesteps S24 to S26 are repeated. If the variable K is greater than 3 (YESin step S26), the first sequence #0 is finished in step S27.

[0210] Similarly to the first sequence #0, when the fourth sequence #3starts being carried out in step S31, all input buffers are causedvacant in step S32.

[0211] Then, a variable K is substituted by 0 and a variable M issubstituted by 0 both in step S33.

[0212] Then, an input buffer to which an allowance to transmit a packetto an output port #M is to be made is selected among vacant inputbuffers in step S34.

[0213] Thereafter, 1 is added to the variable K in step S35. Inaddition, 1 is added to the variable M, and if the variable M is greaterthan 3 (M >3), the variable M is substituted by 0 in step S35.

[0214] Then, the variable K is judged whether greater than 3 (K>3) instep S36. If the variable K is not greater than 3 (NO in step S36), thesteps S34 to S36 are repeated. If the variable K is greater than 3 (YESin step S36), the fourth sequence #3 is finished in step S37.

[0215] Though the second and third sequences #1 and #2 are notillustrated in FIG. 16, they are carried out in a similar manner to thefirst and fourth sequences #0 and #3.

[0216]FIG. 17 is a block diagram of the arbiter circuit used in thefirst embodiment.

[0217] The arbiter circuit 1 is comprised of first to fourth unitmodules 21, 22, 23 and 24 each associated with each of the first tofourth output ports, and a signal line 200 connecting the first tofourth unit modules 21 to 24 to one another in a ring.

[0218] The arbiter circuit 1 carries out the output sequentialarbitration. Each of the first to fourth unit modules 21 to 24 carriesout the basic process for selecting an input buffer in association withan output port. The basic process is carried out in each of the first tofourth unit modules 21 to 24 at the same timing as the basic processescarried out in the above-mentioned input sequential arbitration,ensuring the same advantages as the advantages obtained in the basicprocess in the input sequential arbitration.

[0219]FIG. 18 is a timing chart showing a timing at which each ofsequences is carried out in the input sequential arbitration in themethod of carrying out arbitration in a packet exchanger, in accordancewith the second embodiment.

[0220] In the second embodiment, after a first sequence has beencompleted, a second sequence is carried out. In the second sequence, thebasic processes are carried out in an order just opposite to an order inwhich the basic processes are carried out in the first sequence.

[0221] For instance, in the first sequence #0, the basic processes arecarried out for the input buffers #0, #1, #2 and #3 in this order. Incontrast, in the fifth sequence #4 carried out just after the firstsequence #0, the basic processes are carried out in an order opposite tothe order in the first sequence #0. Specifically, the basic processesare carried out for the input buffers #0, #3, #2 and #1 in this order.

[0222] This arrangement prevents input buffers having a smaller numberfrom preferentially acquiring an allowance to output a packet, ensuringequal opportunity to the input buffers to acquire an allowance to outputa packet.

[0223] Similarly to the first sequence #0, in the second sequence #1,the basic processes are carried out for the input buffers #1, #2, #3 and#0 in this order. In contrast, in the sixth sequence #5 carried out justafter the second sequence #1, the basic processes are carried out forthe input buffers #1, #0, #3 and #2 in this order.

[0224] In the third sequence #2, the basic processes are carried out forthe input buffers #2, #3, #0 and #1 in this order. In contrast, in theseventh sequence #6 carried out just after the third sequence #2, thebasic processes are carried out for the input buffers #2, #1, #0 and #3in this order.

[0225] In the fourth sequence #3, the basic processes are carried outfor the input buffers #3, #0, #1 and #2 in this order. In contrast, inthe eighth sequence #7 carried out just after the fourth sequence #3,the basic processes are carried out for the input buffers #3, #2, #1 and#0 in this order.

[0226] The output buffer sequential arbitration may be defined similarlyto the above-mentioned input sequential arbitration, ensuring the sameadvantages as the advantages obtained by the input sequentialarbitration.

[0227]FIG. 19 is a block diagram of an arbiter circuit used in thesecond embodiment.

[0228] The illustrated arbiter circuit 3 is comprised of first to fourthunit modules 31 to 34 each carrying the said basic processes, a firstsignal line 301 connecting the first to fourth unit modules 31 to 34 toone another in a ring, and a second signal line 302 connecting the firstto fourth unit modules 31 to 34 to one another in a ring.

[0229] A signal is transmitted through the first signal line 301 in afirst direction indicated with an arrow X1, and in contrast, a signal istransmitted through the second signal line 302 in a second directionopposite to the first direction, that is, in a direction indicated withan arrow X2.

[0230] When the basic processes are carried out in a forward order asthe basic processes carried out in the first to fourth sequences #0 to#3, a signal is circulated through the first to fourth unit modules 31to 34 through the first signal line 301. In contrast, when the basicprocesses are carried out in a reverse order as the basic processescarried out in the fifth to eighth sequences #4 to #7, a signal iscirculated through the fourth to first unit modules 34 to 31 through thesecond signal line 302.

[0231]FIG. 20 is a timing chart showing a timing at which each ofsequences is carried out in the input sequential arbitration in themethod of carrying out arbitration in a packet exchanger, in accordancewith the third embodiment.

[0232] In the third embodiment, the sequences #0 to #7 are grouped intoa first group including the sequences #0 to #3 and a second groupincluding the sequences #4 to #7, and an intermission is arrangedbetween the first and second groups.

[0233] Specifically, the sequences #0 to #3 are first concurrentlycarried out. Then, after a unit period of time has been passed, thesequences #4 to #7 are concurrently carried out. In the sequences #0 to#7, an allowance to transmit a packet at different time is made.

[0234] In accordance with the third embodiment, a signal indicative ofinformation relating to vacant output ports can be transmitted throughthe first to fourth unit modules 31 to 34 in a unit period of time as anintermission.

[0235] In the third embodiment, though a sequence takes time twicegreater than the sequence carried out in the first embodiment, it wouldbe possible to transmit a packet at a maximum rate corresponding to aline rate merely by doubling the number of sequences to be concurrentlycarried out.

[0236] The output buffer sequential arbitration may be defined similarlyto the above-mentioned input sequential arbitration, ensuring the sameadvantages as the advantages obtained by the input sequentialarbitration.

[0237]FIG. 21 is a timing chart showing a timing at which each ofsequences is carried out in the output sequential arbitration in themethod of carrying out arbitration in a packet exchanger, in accordancewith the fourth embodiment.

[0238] In the fourth embodiment, cells are grouped into first cellshaving a higher priority and second cells having a lower priority. Inaddition, the basic process to be carried out for each of output portsin each of the first to fourth sequences #0 to #3 is divided into firstand second processes, and each of the first to fourth unit modulesstores the number of first and second cells for the associated outputport.

[0239] In a first half in the basic process, an input buffer to which anallowance to transmit a packet through the associated output port ismade is selected among input buffers accumulating the first cells. Ifsuch an allowance cannot be made to any one of the input buffers, aninput buffer to which an allowance to transmit a packet through theassociated output port is made is selected among input buffersaccumulating the second cells.

[0240] For instance, as illustrated in FIG. 21, the basic processes arecarried out in the following order in the first sequence #0.

[0241] (A) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #0 is made, amonginput buffers accumulating the first cells.

[0242] (B) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #0 is made, amonginput buffers accumulating the second cells.

[0243] (C) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #1 is made, amonginput buffers accumulating the first cells.

[0244] (D) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #1 is made, amonginput buffers accumulating the second cells.

[0245] (E) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #2 is made, amonginput buffers accumulating the first cells.

[0246] (F) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #2 is made, amonginput buffers accumulating the second cells.

[0247] (G) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #3 is made, amonginput buffers accumulating the first cells.

[0248] (H) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #3 is made, amonginput buffers accumulating the second cells.

[0249] The basic processes are carried out in the following order in thesecond sequence #1.

[0250] (A) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #1 is made, amonginput buffers accumulating the first cells.

[0251] (B) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #1 is made, amonginput buffers accumulating the second cells.

[0252] (C) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #2 is made, amonginput buffers accumulating the first cells.

[0253] (D) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #2 is made, amonginput buffers accumulating the second cells.

[0254] (E) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #3 is made, amonginput buffers accumulating the first cells.

[0255] (F) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #3 is made, amonginput buffers accumulating the second cells.

[0256] (G) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #0 is made, amonginput buffers accumulating the first cells.

[0257] (H) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #0 is made, amonginput buffers accumulating the second cells.

[0258] The basic processes are carried out in the following order in thethird sequence #2.

[0259] (A) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #2 is made, amonginput buffers accumulating the first cells.

[0260] (B) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #2 is made, amonginput buffers accumulating the second cells.

[0261] (C) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #3 is made, amonginput buffers accumulating the first cells.

[0262] (D) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #3 is made, amonginput buffers accumulating the second cells.

[0263] (E) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #0 is made, amonginput buffers accumulating the first cells.

[0264] (F) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #0 is made, amonginput buffers accumulating the second cells.

[0265] (G) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #1 is made, amonginput buffers accumulating the first cells.

[0266] (H) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #1 is made, amonginput buffers accumulating the second cells.

[0267] The basic processes are carried out in the following order in thefourth sequence #3.

[0268] (A) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #3 is made, amonginput buffers accumulating the first cells.

[0269] (B) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #3 is made, amonginput buffers accumulating the second cells.

[0270] (C) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #0 is made, amonginput buffers accumulating the first cells.

[0271] (D) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #0 is made, amonginput buffers accumulating the second cells.

[0272] (E) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #1 is made, amonginput buffers accumulating the first cells.

[0273] (F) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #1 is made, amonginput buffers accumulating the second cells.

[0274] (G) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #2 is made, amonginput buffers accumulating the first cells.

[0275] (H) the basic process for selecting an input buffer to which anallowance to transmit a packet through the output port #2 is made, amonginput buffers accumulating the second cells.

[0276] In accordance with the fourth embodiment, even if the first andsecond cells accumulated in different input buffers are addressed to thesame output port, an allowance to be output to the output port iscertainly preferentially given to the first cells having a prioritypreferential to a priority of the second cells.

[0277]FIG. 22 is a timing chart showing a timing at which each ofsequences is carried out in the input sequential arbitration in themethod of carrying out arbitration in a packet exchanger, in accordancewith the fifth embodiment.

[0278] In the fifth embodiment, the basic processes are carried out forall of the input buffers with respect to packets having a higherpriority, and then, the basic processes are carried out for all of theinput buffers with respect to packets having a lower priority.

[0279] In the basic processes carried out with respect to packets havinga higher priority, a search is made as to whether there is an outputport which can transmit a packet having a higher priority therethrough,and if such an output port is found, an allowance to transmit a packetis made to the output port.

[0280] In the fifth embodiment, the basic process is carried out in ahalf of a unit period of time relative to a basic process carried outwith respect to packets having no priority.

[0281] Accordingly, the first to fourth sequences #1 to #3 take the sameperiod of time to be carried out as a period of time necessary for thesequences #0 to #7 in the second embodiment (see FIG. 18) to be carriedout. Thus, it is possible to transmit a packet at a maximum ratecorresponding to a line rate, even if the number of sequences to beconcurrently carried out is not increased.

[0282] In the first sequence #0, the basic processes are carried out forthe input buffers in the following order.

[0283] (A) the basic process for the first input buffer #0 with respectto packets having a higher priority.

[0284] (B) the basic process for the second input buffer #1 with respectto packets having a higher priority.

[0285] (C) the basic process for the third input buffer #2 with respectto packets having a higher priority.

[0286] (D) the basic process for the fourth input buffer #3 with respectto packets having a higher priority.

[0287] (E) the basic process for the first input buffer #0 with respectto packets having a lower priority.

[0288] (F) the basic process for the second input buffer #1 with respectto packets having a lower priority.

[0289] (G) the basic process for the third input buffer #2 with respectto packets having a lower priority.

[0290] (H) the basic process for the fourth input buffer #3 with respectto packets having a lower priority.

[0291] In the second sequence #1, the basic processes are carried outfor the input buffers in the following order.

[0292] (A) the basic process for the second input buffer #1 with respectto packets having a higher priority.

[0293] (B) the basic process for the third input buffer #2 with respectto packets having a higher priority.

[0294] (C) the basic process for the fourth input buffer #3 with respectto packets having a higher priority.

[0295] (D) the basic process for the first input buffer #0 with respectto packets having a higher priority.

[0296] (E) the basic process for the second input buffer #1 with respectto packets having a lower priority.

[0297] (F) the basic process for the third input buffer #2 with respectto packets having a lower priority.

[0298] (G) the basic process for the fourth input buffer #3 with respectto packets having a lower priority.

[0299] (H) the basic process for the first input buffer #0 with respectto packets having a lower priority.

[0300] In the third sequence #2, the basic processes are carried out forthe input buffers in the following order.

[0301] (A) the basic process for the third input buffer #2 with respectto packets having a higher priority.

[0302] (B) the basic process for the fourth input buffer #3 with respectto packets having a higher priority.

[0303] (C) the basic process for the first input buffer #0 with respectto packets having a higher priority.

[0304] (D) the basic process for the second input buffer #1 with respectto packets having a higher priority.

[0305] (E) the basic process for the third input buffer #2 with respectto packets having a lower priority.

[0306] (F) the basic process for the fourth input buffer #3 with respectto packets having a lower priority.

[0307] (G) the basic process for the first input buffer #0 with respectto packets having a lower priority.

[0308] (H) the basic process for the second input buffer #1 with respectto packets having a lower priority.

[0309] In the fourth sequence #3, the basic processes are carried outfor the input buffers in the following order.

[0310] (A) the basic process for the fourth input buffer #3 with respectto packets having a higher priority.

[0311] (B) the basic process for the first input buffer #0 with respectto packets having a higher priority.

[0312] (C) the basic process for the second input buffer #1 with respectto packets having a higher priority.

[0313] (D) the basic process for the third input buffer #2 with respectto packets having a higher priority.

[0314] (E) the basic process for the fourth input buffer #3 with respectto packets having a lower priority.

[0315] (F) the basic process for the first input buffer #0 with respectto packets having a lower priority.

[0316] (G) the basic process for the second input buffer #1 with respectto packets having a lower priority.

[0317] (H) the basic process for the third input buffer #2 with respectto packets having a lower priority.

[0318] In accordance with the fifth embodiment, even if cells having ahigher priority and cells having a lower priority accumulated indifferent input buffers are addressed to the same output port, anallowance to be output to the output port is certainly preferentiallygiven to the cells having a higher priority.

[0319]FIG. 23 is a timing chart showing a timing at which each ofsequences is carried out in the input sequential arbitration in themethod of carrying out arbitration in a packet exchanger, in accordancewith the sixth embodiment.

[0320] In the sixth embodiment, in the first to eighth sequences #0 to#7, the basic processes are carried out for all of the input bufferswith respect to packets having a higher priority, and then, the basicprocesses are carried out for all of the input buffers with respect topackets having a lower priority.

[0321] In accordance with the sixth embodiment, the basic processes arecarried out for all of the input buffers with respect to packets havinga higher priority in the first to fourth sequences #1 to #3, and then,the basic processes are carried out in the fifth to eighth sequences #4to #7.

[0322] In the sixth embodiment, the basic process is carried out in aunit period of time. Hence, though the first to eighth sequences #0 to#7 take a period of time twice greater than a period of time necessaryfor the same sequences in which the basic processes are carried out withrespect to packets having no priority, it would be possible to transmita packet at a maximum rate corresponding to a line rate by doubling thenumber of the sequences to be concurrently carried out.

[0323] In the first sequence #0, the basic processes are carried out inthe following order.

[0324] (A) the basic process for the first input buffer #0 with respectto packets having a higher priority.

[0325] (B) the basic process for the second input buffer #1 with respectto packets having a higher priority.

[0326] (C) the basic process for the third input buffer #2 with respectto packets having a higher priority.

[0327] (D) the basic process for the fourth input buffer #3 with respectto packets having a higher priority.

[0328] (E) the basic process for the first input buffer #0 with respectto packets having a lower priority.

[0329] (F) the basic process for the second input buffer #1 with respectto packets having a lower priority.

[0330] (G) the basic process for the third input buffer #2 with respectto packets having a lower priority.

[0331] (H) the basic process for the fourth input buffer #3 with respectto packets having a lower priority.

[0332] In the second sequence #1, the basic processes are carried out inthe following order.

[0333] (A) the basic process for the second input buffer #1 with respectto packets having a higher priority.

[0334] (B) the basic process for the third input buffer #2 with respectto packets having a higher priority.

[0335] (C) the basic process for the fourth input buffer #3 with respectto packets having a higher priority.

[0336] (D) the basic process for the first input buffer #0 with respectto packets having a higher priority.

[0337] (E) the basic process for the second input buffer #1 with respectto packets having a lower priority.

[0338] (F) the basic process for the third input buffer #2 with respectto packets having a lower priority.

[0339] (G) the basic process for the fourth input buffer #3 with respectto packets having a lower priority.

[0340] (H) the basic process for the first input buffer #0 with respectto packets having a lower priority.

[0341] In the third sequence #2, the basic processes are carried out inthe following order.

[0342] (A) the basic process for the third input buffer #2 with respectto packets having a higher priority.

[0343] (B) the basic process for the fourth input buffer #3 with respectto packets having a higher priority.

[0344] (C) the basic process for the first input buffer #0 with respectto packets having a higher priority.

[0345] (D) the basic process for the second input buffer #1 with respectto packets having a higher priority.

[0346] (E) the basic process for the third input buffer #2 with respectto packets having a lower priority.

[0347] (F) the basic process for the fourth input buffer #3 with respectto packets having a lower priority.

[0348] (G) the basic process for the first input buffer #0 with respectto packets having a lower priority.

[0349] (H) the basic process for the second input buffer #1 with respectto packets having a lower priority.

[0350] In the fourth sequence #3, the basic processes are carried out inthe following order.

[0351] (A) the basic process for the fourth input buffer #3 with respectto packets having a higher priority.

[0352] (B) the basic process for the first input buffer #0 with respectto packets having a higher priority.

[0353] (C) the basic process for the second input buffer #1 with respectto packets having a higher priority.

[0354] (D) the basic process for the third input buffer #2 with respectto packets having a higher priority.

[0355] (E) the basic process for the fourth input buffer #3 with respectto packets having a lower priority.

[0356] (F) the basic process for the first input buffer #0 with respectto packets having a lower priority.

[0357] (G) the basic process for the second input buffer #1 with respectto packets having a lower priority.

[0358] (H) the basic process for the third input buffer #2 with respectto packets having a lower priority.

[0359] The fifth to eighth sequences #4 to #7 are carried out after thebasic processes in the first to fourth sequences #0 to #3 with respectto packets having a higher priority have been completed.

[0360] In the fifth sequence #4, the basic processes are carried out inthe following order.

[0361] (A) the basic process for the first input buffer #0 with respectto packets having a higher priority.

[0362] (B) the basic process for the second input buffer #1 with respectto packets having a higher priority.

[0363] (C) the basic process for the third input buffer #2 with respectto packets having a higher priority.

[0364] (D) the basic process for the fourth input buffer #3 with respectto packets having a higher priority.

[0365] (E) the basic process for the first input buffer #0 with respectto packets having a lower priority.

[0366] (F) the basic process for the second input buffer #1 with respectto packets having a lower priority.

[0367] (G) the basic process for the third input buffer #2 with respectto packets having a lower priority.

[0368] (H) the basic process for the fourth input buffer #3 with respectto packets having a lower priority.

[0369] In the sixth sequence #5, the basic processes are carried out inthe following order.

[0370] (A) the basic process for the second input buffer #1 with respectto packets having a higher priority.

[0371] (B) the basic process for the third input buffer #2 with respectto packets having a higher priority.

[0372] (C) the basic process for the fourth input buffer #3 with respectto packets having a higher priority.

[0373] (D) the basic process for the first input buffer #0 with respectto packets having a higher priority.

[0374] (E) the basic process for the second input buffer #1 with respectto packets having a lower priority.

[0375] (F) the basic process for the third input buffer #2 with respectto packets having a lower priority.

[0376] (G) the basic process for the fourth input buffer #3 with respectto packets having a lower priority.

[0377] (H) the basic process for the first input buffer #0 with respectto packets having a lower priority.

[0378] In the seventh sequence #6, the basic processes are carried outin the following order.

[0379] (A) the basic process for the third input buffer #2 with respectto packets having a higher priority.

[0380] (B) the basic process for the fourth input buffer #3 with respectto packets having a higher priority.

[0381] (C) the basic process for the first input buffer #0 with respectto packets having a higher priority.

[0382] (D) the basic process for the second input buffer #1 with respectto packets having a higher priority.

[0383] (E) the basic process for the third input buffer #2 with respectto packets having a lower priority.

[0384] (F) the basic process for the fourth input buffer #3 with respectto packets having a lower priority.

[0385] (G) the basic process for the first input buffer #0 with respectto packets having a lower priority.

[0386] (H) the basic process for the second input buffer #1 with respectto packets having a lower priority.

[0387] In the eighth sequence #7, the basic processes are carried out inthe following order.

[0388] (A) the basic process for the fourth input buffer #3 with respectto packets having a higher priority.

[0389] (B) the basic process for the first input buffer #0 with respectto packets having a higher priority.

[0390] (C) the basic process for the second input buffer #1 with respectto packets having a higher priority.

[0391] (D) the basic process for the third input buffer #2 with respectto packets having a higher priority.

[0392] (E) the basic process for the fourth input buffer #3 with respectto packets having a lower priority.

[0393] (F) the basic process for the first input buffer #0 with respectto packets having a lower priority.

[0394] (G) the basic process for the second input buffer #1 with respectto packets having a lower priority.

[0395] (H) the basic process for the third input buffer #2 with respectto packets having a lower priority.

[0396] In accordance with the sixth embodiment, even if cells having ahigher priority and cells having a lower priority accumulated indifferent input buffers are addressed to the same output port, anallowance to be output to the output port is certainly preferentiallygiven to the cells having a higher priority.

[0397]FIG. 24 is a block diagram of an arbiter circuit used in the sixthembodiment.

[0398] The illustrated arbiter circuit 4 is comprised of first to fourthunit modules 41 to 44 each carrying out the basic processes, a firstsignal line 401 connecting the first to fourth unit modules 41 to 44 toone another in a ring, and a second signal line 402 connecting first tofourth unit modules 41 to 44 to one another in a ring.

[0399] A signal having a higher priority is transmitted through thefirst signal line 401, and a signal having a lower priority istransmitted through the second signal line 402.

[0400] A signal is transmitted through the first signal line 401 whenthe basic processes are carried out in the sequences with respect topackets having a higher priority. In contrast, a signal is transmittedthrough the second signal line 402 when the basic processes are carriedout in the sequences with respect to packets having a lower priority.Thus, even if the basic processes are carried out in the first to fourthmodules 41 to 44 with respect to both packets having a higher priorityand packets having a lower priority, a signal indicating that the basicprocesses have been completed can be transmitted to the next stage unitmodules.

[0401] The above-mentioned method of carrying out arbitration in apacket exchanger may be accomplished as a program including variouscommands, and be presented through a recording medium readable by acomputer.

[0402] In the specification, the term “recording medium” means anymedium which can record data therein. Examples of a recording medium areillustrated in FIG. 25.

[0403] The term “recording medium” includes, for instance, a disk-shapedrecorder 401 such as CD-ROM (Compact Disk-ROM) or PD, a magnetic tape,MO (Magneto Optical Disk), DVD-ROM (Digital Video Disk-Read OnlyMemory), DVD-RAM (Digital Video Disk-Random Access Memory), a floppydisk 402, a memory chip 404 such as RAM (Random Access Memory) or ROM(Read Only Memory), EPROM (Erasable Programmable Read Only Memory),EEPROM (Electrically Erasable Programmable Read Only Memory), smartmedia (Registered Trade Mark), a flush memory, a rewritable card-typeROM 405 such as a compact flush card, a hard disk 403, and any othersuitable means for storing a program therein.

[0404] A recording medium storing a program for accomplishing theabove-mentioned apparatus may be accomplished by programming functionsof the above-mentioned apparatuses with a programming language readableby a computer, and recording the program in a recording medium such asmentioned above.

[0405] A hard disc equipped in a server may be employed as a recordingmedium. It is also possible to accomplish the recording medium inaccordance with the present invention by storing the above-mentionedcomputer program in such a recording medium as mentioned above, andreading the computer program by other computers through a network.

[0406] As a computer 400, there may be used a personal computer, adesk-top type computer, a note-book type computer, a mobile computer, alap-top type computer, a pocket computer, a server computer, a clientcomputer, a workstation, a host computer, a commercially availablecomputer, and electronic exchanger, for instance.

[0407] While the present invention has been described in connection withcertain preferred embodiments, it is to be understood that the subjectmatter encompassed by way of the present invention is not to be limitedto those specific embodiments. On the contrary, it is intended for thesubject matter of the invention to include all alternatives,modifications and equivalents as can be included within the spirit andscope of the following claims.

[0408] The entire disclosure of Japanese Patent Application No.2000-090444 filed on Mar. 29, 2000 including specification, claims,drawings and summary is incorporated herein by reference in itsentirety.

What is claimed is:
 1. A method of carrying out arbitration in a packetexchanger including an input buffer temporarily storing a packet havingarrived at an input port, and a packet switch which switches a packetbetween a specific input port and a specific output port, said methodcomprising the steps of: (a) concurrently carrying out a first pluralityof sequences in each of said sequences basic processes for at least oneof said input buffer and said output port are carried out in apredetermined order; and (b) making an allowance in each of saidsequences for packets to be output through output ports at differenttimes from one another.
 2. The method as set forth in claim 1 , whereineach of said basic processes includes the step of (c) selecting anoutput port through which a packet is output from an input port, amongoutput ports not yet occupied by any input buffers, said step being tobe carried out in input sequential arbitration in which said basicprocesses are carried out for said input buffers in a predeterminedorder.
 3. The method as set forth in claim 1 , wherein each of saidbasic processes includes the step of selecting an input buffer to beallowed to output a packet through an output port, among input buffersnot yet allowed to do so, said step being to be carried out in outputsequential arbitration in which said basic processes are carried out forsaid output ports in a predetermined order.
 4. The method as set forthin claim 1 , wherein said basic process is completed in a unit period oftime defined as a period of time necessary for said input buffers tooutput a packet, said basic process being carried out for at least oneof said input buffers and said output ports in each of said sequences insaid unit period of time.
 5. The method as set forth in claim 1 ,further comprising the step of concurrently carrying out a secondplurality of sequences after said first plurality of sequences have beencarried out.
 6. The method as set forth in claim 5 , wherein said secondplurality of sequences is carried out in an order just opposite to anorder in which said first plurality of sequences is carried out.
 7. Themethod as set forth in claim 5 , wherein said first plurality ofsequences starts being carried out at a first time and said secondplurality of sequences starts being carried out at a second time laterthan said first time by a predetermined period of time.
 8. The method asset forth in claim 3 , wherein each of said basic processes includes thesteps of: (a) selecting an input buffer to be allowed to output a packethaving a higher priority among packets accumulated in said inputbuffers; and (b) selecting an input buffer to be allowed to output apacket having a lower priority among packets accumulated in said inputbuffers.
 9. The method as set forth in claim 8 , wherein said step (a)is completed in a half of a unit period of time defined as a period oftime necessary for said input buffers to output a packet, and said step(b) is completed in a half of said unit period of time.
 10. The methodas set forth in claim 2 , wherein said step (c) includes the steps of:(c1) carrying out said basic processes for all of said input bufferswith respect to a packet having a higher priority; and (c2) carrying outsaid basic processes for all of said input buffers with respect to apacket having a lower priority.
 11. The method as set forth in claim 10, wherein each of said basic processes is completed in a half of a unitperiod of time defined as a period of time necessary for said inputbuffers to output a packet.
 12. The method as set forth in claim 10 ,wherein each of said basic processes is completed in a unit of period oftime defined as a period of time necessary for said input buffers tooutput a packet, and wherein another sequence starts being carried outafter said step (c1) have been completed.
 13. The method as set forth inclaim 1 , wherein the number of said sequences is equal to the number ofports in said packet exchanger.
 14. An arbiter circuit constituting apacket exchanger together with an input buffer temporarily storing apacket having arrived at an input port, and a packet switch whichswitches a packet between a specific input port and a specific outputport, said arbiter circuit having functions of: (a) concurrentlycarrying out a first plurality of sequences in each of said sequencesbasic processes for at least one of said input buffer and said outputport are carried out in a predetermined order; and (b) making anallowance in each of said sequences for packets to be output throughoutput ports at different times from one another.
 15. The arbitercircuit as set forth in claim 14 , wherein an output port through whicha packet is output from an input port is selected among output ports notyet occupied by any input buffers in each of said basic processes whichare carried out for said input buffers in a predetermined order.
 16. Thearbiter circuit as set forth in claim 14 , wherein an input buffer to beallowed to output a packet through an output port is selected amonginput buffers not yet allowed to do so in each of said basic processeswhich are carried out for said output ports in a predetermined order.17. The arbiter circuit as set forth in claim 14 , wherein said basicprocess is completed in a unit period of time defined as a period oftime necessary for said input buffers to output a packet, said basicprocess being carried out for at least one of said input buffers andsaid output ports in each of said sequences in said unit period of time.18. The arbiter circuit as set forth in claim 14 , wherein said arbitercircuit further includes a function of concurrently carrying out asecond plurality of sequences after carrying out said first plurality ofsequences.
 19. The arbiter circuit as set forth in claim 18 , whereinsaid arbiter circuit carries out said second plurality of sequences inan order just opposite to an order in which said arbiter circuit carriesout said first plurality of sequences.
 20. The arbiter circuit as setforth in claim 18 , wherein said arbiter circuit starts carrying outsaid first plurality of sequences at a first time and said secondplurality of sequences at a second time later than said first time by apredetermined period of time.
 21. The arbiter circuit as set forth inclaim 16 , wherein said arbiter circuit selects an input buffer to beallowed to output a packet having a higher priority among packetsaccumulated in said input buffers, and then selects an input buffer tobe allowed to output a packet having a lower priority among packetsaccumulated in said input buffers, in each of said basic processes. 22.The arbiter circuit as set forth in claim 21 , wherein said arbitercircuit selects said input buffer in a half of a unit period of timedefined as a period of time necessary for said input buffers to output apacket.
 23. The arbiter circuit as set forth in claim 15 , wherein saidarbiter circuit carries out said basic processes for all of said inputbuffers firstly with respect to a packet having a higher priority, andsecondly with respect to a packet having a lower priority.
 24. Thearbiter circuit as set forth in claim 23 , wherein said arbiter circuitcarries out each of said basic processes in a half of a unit period oftime defined as a period of time necessary for said input buffers tooutput a packet.
 25. The arbiter circuit as set forth in claim 23 ,wherein said arbiter circuit carries out each of said basic processes ina unit of period of time defined as a period of time necessary for saidinput buffers to output a packet, and starts carrying out anothersequence after said basic processes have been completed.
 26. The arbitercircuit as set forth in claim 14 , wherein said arbiter circuitincludes: (a) a plurality of unit modules each associated with at leastone of said input buffer and said output port, each of said unit modulescarrying out said basic processes; and (b) a signal line connecting saidunit modules to one another in a ring.
 27. The arbiter circuit as setforth in claim 14 , wherein said arbiter circuit includes: (a) aplurality of unit modules each associated with at least one of saidinput buffer and said output port, each of said unit modules carryingout said basic processes; (b) a first signal line connecting said unitmodules to one another in a ring, a signal being transmitted throughsaid first signal line in a first direction; and (c) a second signalline connecting said unit modules to one another in a ring, a signalbeing transmitted through said second signal line in a second directionopposite to said first direction.
 28. The arbiter circuit as set forthin claim 14 , wherein said arbiter circuit includes: (a) a plurality ofunit modules each associated with at least one of said input buffer andsaid output port, each of said unit modules carrying out said basicprocesses; (b) a first signal line connecting said unit modules to oneanother in a ring, a signal having a higher priority being transmittedthrough said first signal line; and (c) a second signal line connectingsaid unit modules to one another in a ring, a signal having a lowerpriority being transmitted through said second signal line.
 29. Thearbiter circuit as set forth in claim 14 , wherein the number of saidsequences is equal to the number of ports in said packet exchanger. 30.A recording medium readable by a computer, storing a program therein forcausing a computer to carry out a method of carrying out arbitration ina packet exchanger including an input buffer temporarily storing apacket having arrived at an input port, and a packet switch whichswitches a packet between a specific input port and a specific outputport, said method comprising the steps of: (a) concurrently carrying outa first plurality of sequences in each of said sequences basic processesfor at least one of said input buffer and said output port are carriedout in a predetermined order; and (b) making an allowance in each ofsaid sequences for packets to be output through output ports atdifferent times from one another.
 31. The recording medium as set forthin claim 30 , wherein each of said basic processes includes the step of(c) selecting an output port through which a packet is output from aninput port, among output ports not yet occupied by any input buffers,said step being to be carried out in input sequential arbitration inwhich said basic processes are carried out for said input buffers in apredetermined order.
 32. The recording medium as set forth in claim 30 ,wherein each of said basic processes includes the step of selecting aninput buffer to be allowed to output a packet through an output port,among input buffers not yet allowed to do so, said step being to becarried out in output sequential arbitration in which said basicprocesses are carried out for said output ports in a predeterminedorder.
 33. The recording medium as set forth in claim 30 , wherein saidbasic process is completed in a unit period of time defined as a periodof time necessary for said input buffers to output a packet, said basicprocess being carried out for at least one of said input buffers andsaid output ports in each of said sequences in said unit period of time.34. The recording medium as set forth in claim 30 , wherein said methodfurther includes the step of concurrently carrying out a secondplurality of sequences after said first plurality of sequences have beencarried out.
 35. The recording medium as set forth in claim 34 , whereinsaid second plurality of sequences is carried out in an order justopposite to an order in which said first plurality of sequences iscarried out.
 36. The recording medium as set forth in claim 34 , whereinsaid first plurality of sequences starts being carried out at a firsttime and said second plurality of sequences starts being carried out ata second time later than said first time by a predetermined period oftime.
 37. The recording medium as set forth in claim 30 , wherein eachof said basic processes includes the steps of: (a) selecting an inputbuffer to be allowed to output a packet having a higher priority amongpackets accumulated in said input buffers; and (b) selecting an inputbuffer to be allowed to output a packet having a lower priority amongpackets accumulated in said input buffers.
 38. The recording medium asset forth in claim 37 , wherein said step (a) is completed in a half ofa unit period of time defined as a period of time necessary for saidinput buffers to output a packet, and said step (b) is completed in ahalf of said unit period of time.
 39. The recording medium as set forthin claim 31 , wherein said step (c) includes the steps of: (c1) carryingout said basic processes for all of said input buffers with respect to apacket having a higher priority; and (c2) carrying out said basicprocesses for all of said input buffers with respect to a packet havinga lower priority.
 40. The recording medium as set forth in claim 39 ,wherein each of said basic processes is completed in a half of a unitperiod of time defined as a period of time necessary for said inputbuffers to output a packet.
 41. The recording medium as set forth inclaim 39 , wherein each of said basic processes is completed in a unitof period of time defined as a period of time necessary for said inputbuffers to output a packet, and wherein another sequence starts beingcarried out after said step (c1) have been completed.
 42. The recordingmedium as set forth in claim 30 , wherein the number of said sequencesis equal to the number of ports in said packet exchanger.
 43. Arecording medium readable by a computer, storing a program therein forcausing a computer to act as an arbiter circuit constituting a packetexchanger together with an input buffer temporarily storing a packethaving arrived at an input port, and a packet switch which switches apacket between a specific input port and a specific output port, saidarbiter circuit having functions of: (a) concurrently carrying out afirst plurality of sequences in each of said sequences basic processesfor at least one of said input buffer and said output port are carriedout in a predetermined order; and (b) making an allowance in each ofsaid sequences for packets to be output through output ports atdifferent times from one another.
 44. The recording medium as set forthin claim 43 , wherein an output port through which a packet is outputfrom an input port is selected among output ports not yet occupied byany input buffers in each of said basic processes which are carried outfor said input buffers in a predetermined order.
 45. The recordingmedium as set forth in claim 43 , wherein an input buffer to be allowedto output a packet through an output port is selected among inputbuffers not yet allowed to do so in each of said basic processes whichare carried out for said output ports in a predetermined order.
 46. Therecording medium as set forth in claim 43 , wherein said basic processis completed in a unit period of time defined as a period of timenecessary for said input buffers to output a packet, said basic processbeing carried out for at least one of said input buffers and said outputports in each of said sequences in said unit period of time.
 47. Therecording medium as set forth in claim 43 , wherein said arbiter circuitfurther includes a function concurrently carrying out a second pluralityof sequences after carrying out said first plurality of sequences. 48.The recording medium as set forth in claim 47 , wherein said arbitercircuit carries out said second plurality of sequences in an order justopposite to an order in which said arbiter circuit carries out saidfirst plurality of sequences.
 49. The recording medium as set forth inclaim 47 , wherein said arbiter circuit starts carrying out said firstplurality of sequences at a first time and said second plurality ofsequences at a second time later than said first time by a predeterminedperiod of time.
 50. The recording medium as set forth in claim 45 ,wherein said arbiter circuit selects an input buffer to be allowed tooutput a packet having a higher priority among packets accumulated insaid input buffers, and then selects an input buffer to be allowed tooutput a packet having a lower priority among packets accumulated insaid input buffers, in each of said basic processes.
 51. The recordingmedium as set forth in claim 50 , wherein said arbiter circuit selectssaid input buffer in a half of a unit period of time defined as a periodof time necessary for said input buffers to output a packet.
 52. Therecording medium as set forth in claim 44 , wherein said arbiter circuitcarries out said basic processes for all of said input buffers firstlywith respect to a packet having a higher priority, and secondly withrespect to a packet having a lower priority.
 53. The recording medium asset forth in claim 52 , wherein said arbiter circuit carries out each ofsaid basic processes in a half of a unit period of time defined as aperiod of time necessary for said input buffers to output a packet. 54.The recording medium as set forth in claim 52 , wherein said arbitercircuit carries out each of said basic processes in a unit of period oftime defined as a period of time necessary for said input buffers tooutput a packet, and starts carrying out another sequence after saidbasic processes have been completed.
 55. The recording medium as setforth in claim 53 , wherein said arbiter circuit includes: (a) aplurality of unit modules each associated with at least one of saidinput buffer and said output port, each of said unit modules carryingout said basic processes; and (b) a signal line connecting said unitmodules to one another in a ring.
 56. The recording medium as set forthin claim 53 , wherein said arbiter circuit includes: (a) a plurality ofunit modules each associated with at least one of said input buffer andsaid output port, each of said unit modules carrying out said basicprocesses; (b) a first signal line connecting said unit modules to oneanother in a ring, a signal being transmitted through said first signalline in a first direction; and (c) a second signal line connecting saidunit modules to one another in a ring, a signal being transmittedthrough said second signal line in a second direction opposite to saidfirst direction.
 57. The recording medium as set forth in claim 53 ,wherein said arbiter circuit includes: (a) a plurality of unit moduleseach associated with at least one of said input buffer and said outputport, each of said unit modules carrying out said basic processes; (b) afirst signal line connecting said unit modules to one another in a ring,a signal having a higher priority being transmitted through said firstsignal line; and (c) a second signal line connecting said unit modulesto one another in a ring, a signal having a lower priority beingtransmitted through said second signal line.
 58. The recording medium asset forth in claim 53 , wherein the number of said sequences is equal tothe number of ports in said packet exchanger.